Highlights

• Cadence Tempus Timing Solution and Quantus Extraction Solution enabled Samsung Foundry to confidently sign off their SF5A design while achieving optimal PPA results
• As a result of their first deployment of Cadence signoff solutions, Samsung Foundry realized a 2X productivity boost for faster design closure

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence^® Quantus^™ Extraction Solution and Tempus^™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.

One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus^™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.

“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics, Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”

“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”

The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design^™ strategy, enabling customers to achieve SoC design excellence. For more information, please visit www.cadence.com/go/signoffsfcs.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

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Category: Featured

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