PLX Expert Chosen for DesignCon Panel to Address PCI Express Gen3 Test, Measurement
SUNNYVALE, CA -- (Marketwire) -- 01/17/12 -- PLX Technology, Inc. (NASDAQ: PLXT), a leader in high-speed connectivity solutions for the enterprise data center, today announced Reginald Conley, PLX® director of hardware applications, will be among the distinguished panelists for a DesignCon 2012 session focused on measuring high-speed serial architectures. Conley will address PCI Express (PCIe) Gen3 and how its speed -- 8GBps, per lane -- can be optimized and verified through special integrated on-chip diagnostics tools and software, as well as via major test and measurement equipment.
The panel discussion, titled The Future of Measurements (Session 13-TP7), takes place Jan. 31, 3:45 p.m., at the Santa Clara Convention Center, in Santa Clara, Calif.
As applications director, Conley has overseen PLX PCIe switching products' successful penetration into high-speed system designs worldwide and in virtually all market segments. He's authored several articles on PCIe and also hosted tutorial videos explaining the interconnect technology's prominence and future in powerful system designs requiring speed and versatility:
"DesignCon 2012 provides an ideal forum to address not just how PCI Express provides the interconnect backbone of high-speed designs but also how designers can glean valuable metrics of its performance, through sophisticated equipment and advanced on-chip features," said Conley. "Designing with PCI Express Gen3 poses both opportunities and challenges for design engineers -- such as selecting the appropriate switch for a particular application, and assuring it interoperates optimally with other system components -- so it's crucial those designers be informed on the dynamics of test and measurement early in the design stage."
PLX was selected to take part in the panel due to its strong market position, history of innovation and extensive portfolio of ExpressLane PCIe switches with unique on-chip testing capabilities. These switches are supported by PLX's exclusive visionPAK system debug tools, such as Performance Monitoring, Error Injection, Packet Generator, and the ability to measure both width and height of a SerDes eye using PLX's free software development kit (SDK). The on-chip hardware debug features, complemented by the SDK, offer instant logic analyzer support, high-speed scope view, pattern generation, and error injection -- all capabilities that work in conjunction with existing equipment, and in many cases eliminate the need to purchase new, high-cost test systems. Used by OEMs worldwide for thousands of PCIe-based products, the PLX SDK reduces validation tool budgets and helps products get to market faster.
With a dominant 68 percent market share and first-to-market leadership, PLX is the world's premier supplier of PCIe switching solutions. The company's vast portfolio of ExpressLane PCIe Gen1, Gen2 and industry-first, production-ready Gen3 devices provide designers worldwide with more than 40 highly configurable, low-power, low-latency PCIe switches, all backed by free productivity- and performance-enhancing development software.
For more information on PLX PCIe Gen3 switches, go to www.plxtech.com/gen3.
For more information on and to register for DesignCon 2012, go to www.designcon.com/how_to_register.
About PLX Technology
PLX Technology, the PLX Technology logo and ExpressLane are trademarks or registered trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Other names and brands may be claimed as the property of others.
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