Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced Fan-Out Chip-on-Substrate-Bridge (FOCoS-Bridge) with Through Silicon Via (TSV), propelling technology enablement for artificial intelligence (AI) and its pervasive impact on global life. Delivering critical performance improvements, ASE’s FOCoS-Bridge with TSV addresses growing demand for increased bandwidth by creating a shorter delivery path through TSV and enabling a higher I/O density and enhanced thermal dissipation. The integration of TSV expands ASE’s VIPack™ FOCoS-Bridge capabilities to deliver critical energy efficiency at a time when the need has never been greater across emerging AI and high-performance computing (HPC) applications.

Future chiplet and high-bandwidth memory (HBM) integration will require higher interconnection densities to accommodate parallel higher data rate links and to preserve signal integrity. High-density interconnection is a key enabler of chiplet integration. AI and HPC power delivery requirements are becoming more complex and now necessitate advanced bridge chips with TSV features. The VIPack FOCoS-Bridge platform can be utilized for embedding passives and active dies, which can help improve power integrity and provide direct access for improved performance.

“Artificial intelligence is increasingly integrated across a broad spectrum of applications—from intelligent manufacturing systems and autonomous vehicles to next-generation retail infrastructure and precision medical diagnostics—driving exponential growth in computational requirements and energy efficiency demands,” said Yin Chang, Executive Vice President at ASE. “Our introduction of the FOCoS-Bridge with TSV underscores ASE's strategic commitment to supporting the AI ecosystem with advanced heterogeneous integration solutions. This innovation enhances our VIPack portfolio, offering a scalable, high-density packaging platform optimized for sustainable, high-performance computing architectures.”

The expansion of ASE’s VIPack platform reflects the company’s strategic vision to provide a comprehensive, scalable ecosystem for sustainable, high-performance computing that meets the rigorous demands of emerging AI workloads. ASE’s FOCoS-Bridge with TSV can fulfill next-generation AI and HPC performance demands through heterogenous integration for high-power and high-bandwidth systems. Progress has been demonstrated using an 85mm x 85mm test vehicle comprised of two identical fan-out modules. Each module is made up of one ASIC chip and four HBM3 chips that are laterally interconnected with four TSV bridge chips, as well as 10 integrated passive device chips.

The TSV bridge chips provide a new shorter vertical path for power delivery in conjunction with traditional lateral signal connections. The TSV and passive devices are embedded and interconnected using three redistribution layers (RDLs) with 5µm line and space. When compared to FOCoS-Bridge, the resistance and inductance of FOCoS-Bridge TSV are significantly reduced by 72% and 50%, respectively.

“The growing demands of HPC and AI applications are accelerating the need for greater computational performance, and ASE’s FOCoS-Bridge capabilities enable seamless integration of SoCs and chiplets with high-bandwidth memory,” said Teck Lee, Director of R&D at ASE. “By incorporating TSV, FOCoS-Bridge enhances compute and energy efficiency, and elevates our advanced packaging portfolio to the next level.”

FOCoS-Bridge technology has already demonstrated its ability to address higher bandwidth and faster data transfer rates in AI and HPC applications. It leverages the advantages of highly integrated fan-out structures to overcome the limitations of traditional electrical interconnects, and enables high-speed, low-latency, and energy-efficient data communication between processors, accelerators, and memory modules. While establishing the foundation for embedding passives and active chips in the fan-out package, FOCoS-Bridge also provides options of decoupling capacitor integration for power delivery optimization and active dies for interconnection between to certain functions, such as memory, I/O, and more.

“ASE is strategically positioned at the forefront of the industry as a premier provider of advanced packaging solutions for high-power AI and high-performance computing applications,” said Charles Lee, Director of Engineering and Technical Promotion at ASE. “Our strength lies in our ability to deliver innovative technologies that address customers’ evolving needs in a rapidly advancing market.”

ASE will participate at ECTC 2025 in Dallas, May 27-30, 2025, with an exhibition showcasing our VIPack technologies, while delivering a suite of technologist presentations and panelist opinion across the conference program.

Supporting resources

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• For more on ECTC 2025: https://www.ectc.net/program/

About ASE, Inc.

ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, automotive, 5G, high-performance computing, and more. To learn about our advances in SiP, fan-out, MEMS & sensor, flip chip, and 2.5D, 3D & TSV technologies, all ultimately geared toward applications to improve lifestyle and efficiency, please visit: aseglobal.com, or follow us on LinkedIn & X: @aseglobal.

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Our introduction of the FOCoS-Bridge with TSV underscores ASE's strategic commitment to supporting the AI ecosystem with advanced heterogeneous integration solutions.