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For more than 30 years, Cabling Installation & Maintenance has provided useful, practical information to professionals responsible for the specification, design, installation and management of structured cabling systems serving enterprise, data center and other environments. These professionals are challenged to stay informed of constantly evolving standards, system-design and installation approaches, product and system capabilities, technologies, as well as applications that rely on high-performance structured cabling systems. Our editors synthesize these complex issues into multiple information products. This portfolio of information products provides concrete detail that improves the efficiency of day-to-day operations, and equips cabling professionals with the perspective that enables strategic planning for networks’ optimum long-term performance.

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Cadence Announces Full DRAM Verification Solution for Automotive, Data Center, and Mobile Applications

By: via Business Wire

Highlights:

  • New solution accelerates IP-to-SoC-level verification for complex memory controllers, PHYs and devices for LPDDR5x, DDR5, HBM3 and GDDR6 protocols
  • Up to 10X increase in verification throughput enables total IP-to-SoC-level verification of advanced designs with multiple DDR interfaces

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10X increased verification throughput, customers can quickly and effectively perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces.

Modern SoC designs leverage advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard as well as SoC-level verification to meet application-specific system performance definitions and data and cache coherency requirements.

“DRAM memory verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, in the System & Verification Group at Cadence. “With the industry’s first full DRAM verification solution, we’re enabling our customers to verify their IP designs effectively and ensure their designs comply with the JEDEC standard specification as well as the memory subsystem application-specific performance metrics to provide the fastest path to IP and system verification closure.”

The new DRAM verification solution enables IP-level verification through Cadence® PHY VIPs and memory models with a direct and seamless path to SoC-level verification with the Cadence System VIP solution, including the System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, enabling fast and efficient memory subsystem and SoC verification for simulation and emulation environments.

The solution also includes Cadence TripleCheck™ technology, which provides users with a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification.

“Micron is committed to leading the development of next-generation memory technologies that drive value from the data center to the intelligent edge and across client and mobile user experiences,” said Malcolm Humphrey, vice president and general manager of the Compute DRAM Products Group at Micron. “Our collaboration with Cadence accelerates ecosystem development to deliver innovative memory solutions.”

The new verification solution for DRAM verification is part of the broader Cadence verification full flow, which includes Palladium® Z2 emulation, Protium™ X2 prototyping, Xcelium™ simulation, the Jasper® Formal Verification Platform, the Helium™ Virtual and Hybrid Studio, and the vManager™ Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The DRAM verification solution and verification full flow support the company’s Intelligent System Design™ strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/DRAMVerification.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.

Category: Featured

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