SAN JOSE, Calif., Oct. 13, 2025 (GLOBE NEWSWIRE) -- Astera Labs, Inc. (Nasdaq: ALAB), a leader in semiconductor-based connectivity solutions for rack-scale AI infrastructure, today announced from the 2025 OCP Global Summit comprehensive ecosystem collaborations that demonstrate growing industry momentum around open standards for AI Infrastructure 2.0—where entire racks function as unified computing platforms rather than collections of individual servers. Through live demonstrations and technical sessions, Astera Labs will showcase the breadth of support for solutions built with PCIe, UALink, Ethernet, CXL, and OpenBMC standards.
“The AI infrastructure landscape is rapidly evolving from server-level architectures to rack-scale systems operating as unified compute platforms,” said Patrick Moorhead, CEO and chief analyst at Moor Insights & Strategy. “As hyperscalers invest billions in next-generation infrastructure, open standards are critical to providing the flexibility needed to integrate diverse accelerators, interconnects, rack designs, and management tools—enabling fully optimized solutions for specialized AI workloads.”
These ecosystem collaborations are building momentum across key areas of rack-scale deployments:
- GPU and CPU connectivity for optimal compute performance
- Advanced cabling and connector solutions for robust signal integrity
- ODM manufacturing expertise for scalable deployment
- Intelligent management solutions for operational efficiency
- Comprehensive design enablement tools for faster market adoption
"Our approach to realizing AI Infrastructure 2.0 is simple: collaborate, standardize, and accelerate. Because when the ecosystem works together, innovation happens faster," said Sanjay Gajendra, president and chief operating officer of Astera Labs. "Whether it's GPU interoperability, manufacturing expertise, or rack-scale management—we are delivering intelligent connectivity for the AI workloads of today and tomorrow.”
At OCP Global Summit 2025, Astera Labs' technical experts are presenting six sessions covering topics including UALink deployment strategies and PCIe 6 security considerations, while live demos at Booth #B33 highlight rack-scale AI connectivity solutions. Visit www.asteralabs.com/about/events/ocp2025 for the complete schedule or stop by Booth #B33 to experience these innovations firsthand.
Ecosystem Support
Danny Moore, Director, AI Technology and Ecosystems at AMD
“The future of AI infrastructure depends on an open ecosystem that enables customers to choose the best AI accelerator for their specific workloads. Our collaboration with Astera Labs on UALink connectivity ensures our joint customers can deploy AMD Instinct GPUs at scale in open rack architectures that deliver performance, energy efficiency and flexibility.”
Mark St. Hilaire, General Manager of Amphenol High Speed Cables
“Designing and manufacturing high-performance cables for AI infrastructure requires deep collaboration with silicon connectivity providers. Our relationship with Astera Labs will ensure customers have access to reliable, high-speed cable solutions that extend Astera Labs' connectivity capabilities from board-level to rack-scale deployments with supply chain diversity.”
Mohamed Awad, Senior Vice President and General Manager, Infrastructure Business, Arm
“AI infrastructure is rapidly evolving into tightly integrated systems that demand accelerated performance, power efficiency, and design flexibility. Our collaboration with Astera Labs is helping hyperscalers significantly boost performance of AI systems with Neoverse-based CPUs and GPUs via high-bandwidth scale up connectivity solutions.”
Chris Lin, Chairman and President at ASPEED
“In collaboration with Astera Labs, we’ll be delivering a standards-based management and monitoring stack on OCP hardware that hyperscalers can seamlessly integrate into monitoring systems, extend across fleet orchestration layers, and leverage to maximize ROI from AI infrastructure. This relationship demonstrates our commitment to an open, interoperable ecosystem that accelerates deployment and ensures reliability at rack-scale.”
Ashutosh Mauskar, Vice President, Product Management, Custom Systems Design and Analysis Products at Cadence Design Systems
"When you're pushing signals at PCIe 6 speeds across a rack full of different vendors' chips, the analog design becomes absolutely critical - one poorly designed power rail or signal path can cripple performance for the entire system. Our collaboration with Astera Labs gives engineers the analog simulation and verification tools to get these high-speed connections right the first time, because at rack scale, there's no room for signal integrity surprises."
Sean Davies, Vice President of Sales at Eoptolink
"Advanced optical connectivity becomes essential as AI infrastructure scales beyond traditional rack boundaries. Working with Astera Labs, we'll integrate their connectivity intelligence with our advanced optical transceivers to deliver power-efficient, high-bandwidth solutions that maintain signal integrity across the extended distances required for modern AI data center architectures.”
Ingrasys
“Hyperscalers must accelerate time-to-market to keep pace with rapidly expanding scale and capacity demands of new AI models. Our global AI server manufacturing and rack-scale integration capabilities accelerate next-generation AI computing solutions, and working with Astera Labs, we deliver integrated connectivity support that addresses customers' scale, performance, and time-to-market requirements.”
Jeffrey Wang, President at Insyde Software
“OpenBMC has emerged as the de facto standard for platform management, and our collaboration with Astera Labs extends this proven framework to next-generation connectivity fabrics. By enabling standardized API support for retimers and scale-up switches, we will empower our mutual customers to accelerate AI infrastructure deployments with confidence—knowing their management and monitoring stack is rooted in open standards, validated at hyperscale, and ready for the future.”
Chad Jameson, General Manager, IO Solutions at Molex
"By working closely with Astera Labs, we're optimizing cable and connector solutions for the latest standards like PCIe 6 and UALink 1.0 supporting 200G. Our complementary technologies work together to ensure robust signal integrity across rack-scale distances. This approach delivers high-value connectivity solutions while providing the supply chain diversity that enables customer flexibility in large-scale deployments."
Mike Yang, Executive Vice President of Quanta Computer Inc. and President of QCT
"Rack-scale AI infrastructure demands manufacturing precision and supply chain reliability that can only be achieved through close ecosystem partnerships. Our collaboration with Astera Labs ensures that customers receive validated, production-ready solutions that meet the demanding requirements of modern AI workloads."
Neeraj Paliwal, Senior Vice President of IP Product Management at Synopsys
“Synopsys has a strong track record of delivering robust, silicon-proven IP and verification tools that enable industry leaders developing next-generation SoCs to adopt emerging interface standards with seamless interoperability across the ecosystem. Our collaboration with Astera Labs brings essential technologies to the ecosystem, accelerating the adoption of open rack architectures and enabling customers to achieve performance, interoperability, and scalability at rack scale.”
Pranav Garg, Vice President, Strategy, Business Development and Marketing, Digital Data Networks Business Unit at TE Connectivity
“Our collaboration with Astera Labs extends beyond traditional cable assemblies to integrated backplane solutions that embed Aries retimer technology directly into the rack infrastructure. By incorporating Astera Labs’ intelligent retimers into our active backplane designs, we’re delivering increased density and reliable rack-scale connectivity while maintaining the high-speed performance for demanding AI workloads.”
Pen Wei Wu, Vice President of Enterprise & Networking Business Group at Wistron
“Innovation in AI system design requires close collaboration between connectivity providers and system manufacturers. Working with Astera Labs, Wistron is committed to delivering excellent and reliable manufactured products for hyperscale deployments.”
Steven Hsieh, Vice President at Wiwynn
"Next-generation AI demands rack-level integration that unifies connectivity and performance across systems. Our collaboration with Astera Labs delivers high-density rack architectures that maximize connectivity efficiency, enabling hyperscale customers to operate the entire rack as a single high-performance computing unit.”
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.
Forward-Looking Statements
This communication contains certain forward-looking statements regarding Astera Lab’s comprehensive ecosystem collaborations, the momentum they will continue building in the industry around open standards, the expectations of the multiple collaborations and their anticipated impact and benefits. Such forward-looking statements may be introduced using words such as “building,” “can,” “committed,” “ensures,” “growing,” “momentum,” “tomorrow,” “we’ll,” “will” and variations of such words and similar expressions. Such statements involve risks and uncertainties, many of which are beyond the control of Astera Labs and its collaboration partners, that could cause actual results to differ materially from those expressed or implied in the forward-looking statements, including, among others, the risk that we may be unable to successfully implement the collaborations or combine Astera Lab’s expertise and products with those of its collaboration partners; the expected benefits of the collaboration may not be realized; delays, disruptions, challenges or increased costs in the solutions covered by the collaborations; the complexities and uncertainties in developing and implementing solutions based on new technologies; the momentum that the collaborations are building around open standards ceases or diminishes; litigation or disputes related to the collaborations or otherwise; macroeconomic conditions, including general semiconductor industry economic conditions; regulatory restrictions; international conflict and other risks and uncertainties described in Astera Lab’s Form 10-K, Form 10-Q and other SEC filings. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise, except to the extent that disclosure may be required by law.
Press Contact:
Peter Lo
peter.lo@asteralabs.com
