The global semiconductor industry is entering a new inflection point. The explosive growth of artificial intelligence, the continuous evolution of mobile computing, and the rapid rise of intelligent automotive systems are placing unprecedented demands on chip performance and energy efficiency. Amid this transformation, MediaTek has held the top position in the global smartphone application processor market for multiple consecutive years, driven by its Dimensity Mobile SOC platforms.
At the center of that success stands one technical leader who has spent more than a decade refining a single core idea: dynamic configuration. He has translated it into a foundational technology that has reshaped the mobile computing experience. That engineer is Tsao Youming, Associate General Manager at MediaTek whom leads the GPU and Computing System Technology.
Breaking the Heterogenous Computing Deadlock: The Birth of Dynamic Configuration Cache
The rise of mobile multi-cores, multi-domains processors once threw the industry into collective anxiety. As octa-core CPU, GPU and NPU chips entered smartphones, chip designers discovered that traditional static architectures were ill-equipped to manage these performance powerhouses. Resource contention between cores and other processors, the complexity of cache coherency, and the strict power constraints of portable devices formed a trilemma that seemed impossible to resolve.
"We faced a fundamental problem: how to let multi-core, multi-domains processors run at full speed on a phone without heat buildup crashing the system," Tsao recalled. As one of the earliest engineers working on mobile multi-core architecture, he recognized that dynamically allocating hardware resources would become the defining competitive advantage for mobile chips. At the time, the industry norm was fixed cache mapping and static voltage-frequency adjustment, a one-size-fits-all approach that proved clumsy and inefficient in multi-core scenarios.
Tsao set out to rebuild the system architecture from the ground up. He led the development of the patent technology known as "Method and Apparatus for Performing Dynamic Configuration," targeting the deepest bottlenecks of mobile multi-core processing. The challenge was formidable: achieving OS-level virtualization-like resource scheduling in hardware, while meeting the stringent real-time requirements of embedded systems.
The Critical Breakthrough: Bus Freezing and Cache Reconstruction
The first major obstacle was the atomicity of configuration switching. When dynamically adjusting cache partitions, how could data consistency across multiple cores be guaranteed? Early software-based synchronization protocols carried too much latency overhead to meet real-time requirements.
Tsao proposed a bold solution: a bus-freezing mechanism. By briefly freezing bus communication between the dynamic configuration cache and the processors during reconfiguration, the system could enforce atomic configuration operations. The idea sparked heated internal debate. Would freezing the bus cause system stuttering? How would suspended processor requests be handled?
"We spent three full months on simulation and validation," Tsao said. "We designed a tiered freeze strategy. Rather than simply cutting the bus, we first broadcast a freeze signal so each core could complete its current transaction and enter standby before the configuration switch executed." This hardware handshake protocol reduced configuration-switching latency to the microsecond range, making it virtually imperceptible to users.
Another major challenge was dynamic partition management of on-chip memory. Traditional caches use fixed physical mapping, but Tsao's approach required runtime repartitioning of cache regions, necessitating entirely new address mapping tables and access control logic within constrained chip area. The team developed a virtual partition architecture that abstracted physical cache into dynamically reorganizable logical units, enabling processors to flexibly access compute resources based on real-time workloads.
From Theory to Industry: The Architecture Evolution
Over more than a decade, Tsao continuously advanced this technology toward commercialization. Currently, most of the Flagship Smartphone SOCs adopt similar concept such as Apple’s A19 SOC with System Level Cache. The the Dimensity 9500 flagship chip released last September, the technology's value was fully validated. The dynamic cache system manages the system level cache configuration at the hardware level, achieving a 14% reduction in power consumption during 120fps gaming versus the prior generation. The coherence engine dramatically reduced and stabilized touch response latency, delivering a smooth experience with every interaction. These gains are underpinned by the flexible hardware-level scheduling that dynamic configuration provides.
"When we were brought the prototype features in the lab, none of us imagined this technology would one day power flagship chips shipping in the tens of millions," Tsao reflected. From early multi-core/mutl-domain scheduling to the CPU+GPU+NPU intelligent management of the Dimensity 9500, the dynamic configuration concept has evolved completely from hardware cache layers up to system scheduling layers.
Building a Technology Legacy
Today, Tsao leads more than 200 engineers in GPU IP development and over 40 in computing system architecture. The technology he pioneered not only solved the Heterogeneous Computing Architecture challenges of an earlier era, but established an extensible foundation for the continued evolution of mobile computing.
Before his work, the industry widely assumed resource scheduling on mobile devices should be handled by software. Tsao proved through hardware architecture innovation that foundational flexibility is the bedrock of the user experience built above it. In an era of intensifying global semiconductor competition, his journey demonstrates that sustained investment in foundational architecture ultimately translates into core product competitiveness, from solving multi-core integration challenges to enabling a 3-nanometer flagship chip, in relentless pursuit of the optimal balance between performance and power efficiency.
(By Wu Junlin)
Media Contact
Company Name: MediaTek Inc.
Contact Person: Tsao Youming
Email: Send Email
Country: Taiwan
Website: https://www.linkedin.com/in/eddie-tsao-b761b890/
