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For more than 30 years, Cabling Installation & Maintenance has provided useful, practical information to professionals responsible for the specification, design, installation and management of structured cabling systems serving enterprise, data center and other environments. These professionals are challenged to stay informed of constantly evolving standards, system-design and installation approaches, product and system capabilities, technologies, as well as applications that rely on high-performance structured cabling systems. Our editors synthesize these complex issues into multiple information products. This portfolio of information products provides concrete detail that improves the efficiency of day-to-day operations, and equips cabling professionals with the perspective that enables strategic planning for networks’ optimum long-term performance.

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Astera Labs and Alchip Announce Strategic Partnership to Advance Silicon Ecosystem for AI Rack-Scale Connectivity

SANTA CLARA, Calif. and TAIPEI, Taiwan, June 16, 2025 (GLOBE NEWSWIRE) -- Astera Labs, a leading provider of purpose-built connectivity solutions for AI and cloud infrastructure, and Alchip Technologies, the high-performance ASIC leader, today announced a strategic partnership to advance the silicon ecosystem for next generation AI infrastructure. The collaboration combines Alchip's custom ASIC development capabilities with Astera Labs' comprehensive connectivity portfolio to deliver validated, interoperable solutions for hyperscalers building next-generation AI infrastructure.

"Our vision is to be the rack-level connectivity partner for hyperscalers," said Sanjay Gajendra, president and chief operating officer, Astera Labs. "As custom compute platforms evolve to rack-scale implementations requiring advanced scale-up and scale-out connectivity, our partnership with Alchip will empower hyperscalers to seamlessly deploy complex AI infrastructure with a multitude of interconnect technologies, shorten time-to-market, and reduce integration risks."

Hyperscalers face critical challenges in the AI infrastructure ecosystem as models scale to unprecedented sizes and complexity. Modern AI deployment requires rack-level solutions that integrate custom compute accelerators with high-performance connectivity fabrics, delivered within compressed development windows.

"The convergence of custom silicon and advanced connectivity is reshaping how AI infrastructure is architected and deployed," said Johnny Shen, president and chief executive officer, Alchip Technologies. "Our collaboration with Astera Labs creates a powerful resource that will deliver complete solutions hyperscalers need to efficiently implement AI workloads at scale. Together, we're streamlining purpose-built AI infrastructure that meets the performance and scale demands of next-generation applications."

Hyperscalers will benefit from this strategic partnership with validated total solutions that combine Alchip's ASIC design expertise and Astera Labs' Intelligent Connectivity Platform which includes the COSMOS software suite. The partnership also advances industry innovation for next-generation AI connectivity standards including CXL®, Ethernet, NVLink Fusion, PCIe®, and UALink™, increasing options and strengthening the overall ecosystem.

About Astera Labs
Astera Labs advances next-generation AI infrastructure through purpose-built connectivity solutions to solve data, network, and memory bottlenecks at a rack-scale. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based solutions with the company's COSMOS software suite to unify diverse components into cohesive, scalable systems with unprecedented rack-level observability and data center fleet management capabilities. By collaborating with hyperscalers, standards organizations, and partners, Astera Labs promotes a scalable AI infrastructure developed within open ecosystems and robust supply chains. Discover more at http://www.asteralabs.com.

About Alchip
Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon design and production services for system companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technologies. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3DIC design, CoWoS/chiplet design and manufacturing management. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).

This press release contains forward-looking statements within the meaning of the federal securities laws that involve risks and uncertainties. Forward-looking statements include, without limitation, any statement that may predict, forecast, indicate or imply future events, results or achievements. Actual events, results or achievements may differ materially from those contemplated in this press release. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in Astera Lab’s Form 10-K, Form 10-Q and other filings with the SEC. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise, except to the extent that disclosure may be required by law.

Media Contacts

Peter Lo
Peter.lo@asteralabs.com
+1-858-209-1896

Chuck Byers
chuck_byers@alchip.com
+1-408-310-9244


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