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Editorial Advisory Board

  • Professor Andrea M. Armani, University of Southern California
  • Ruti Ben-Shlomi, Ph.D., LightSolver
  • James Butler, Ph.D., Hamamatsu
  • Natalie Fardian-Melamed, Ph.D., Columbia University
  • Justin Sigley, Ph.D., AmeriCOM
  • Professor Birgit Stiller, Max Planck Institute for the Science of Light, and Leibniz University of Hannover
  • Professor Stephen Sweeney, University of Glasgow
  • Mohan Wang, Ph.D., University of Oxford
  • Professor Xuchen Wang, Harbin Engineering University
  • Professor Stefan Witte, Delft University of Technology

Teradyne Awarded 2025 TSMC Open Innovation Platform® (OIP) Partner of the Year for TSMC 3DFabric® Testing

Teradyne, Inc. (NASDAQ: TER), a leading provider of automated test equipment and advanced robotics, is proud to announce it has been recognized as the 2025 TSMC Open Innovation Platform® (OIP) Partner of the Year for TSMC 3DFabric® Testing. This recognition reflects the strong collaboration between Teradyne, TSMC and the larger OIP ecosystem.

Through the TSMC OIP 3DFabric Alliance, Teradyne worked closely with TSMC, the world’s leading semiconductor foundry, to pioneer multi-die test methodologies for chiplets and TSMC CoWoS® advanced packaging technology. These efforts have significantly improved silicon bring-up efficiency and elevated test quality – marking a key milestone in our industry’s transition to chiplet-based architectures.

“At Teradyne, we strongly believe in the open and collaborative ecosystem approach of TSMC’s Open Innovation Platform and look forward to continuing our partnership to drive innovation and deliver exceptional value to our customers,” said Shannon Poulin, President, Semiconductor Test Group at Teradyne. “Teradyne’s strategic investments in UCIe, GPIO, and streaming scan test solutions enable scalable, high-quality testing across die-to-die interfaces. For our customers, this means faster time to revenue for the complex 3D ICs used in demanding AI and cloud datacenter applications.”

Teradyne’s comprehensive portfolio of semiconductor and electronics test equipment supports today’s demanding devices and emerging chip architectures across all test insertions, while this innovation enables high-speed scan testing over UCIe die-to-die interfaces at wafer sort or chip probing. Enhancing high-speed test coverage for UCIe interfaces reduces defect escapes, improves the overall cost of quality, and enables faster time-to-market for these complex 3D semiconductors used in AI and cloud datacenter applications.

“We congratulate Teradyne for their contributions to the OIP ecosystem, driving innovations that improve silicon bring-up and test quality,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. “Our long-standing partnership and collaborative efforts with OIP ecosystem partners like Teradyne enable our customers to accelerate AI proliferation through innovations in high performance, energy-efficient compute, leveraging test tools and methodologies that shorten time-to-market.”

The award was announced at the 2025 TSMC North America OIP Ecosystem Forum, held in Santa Clara, California, on September 24, 2025. This year’s event brought together TSMC’s semiconductor design partners and customers to highlight how the ecosystem is harnessing the immense potential of AI in the next generation of design solutions for TSMC’s advanced process and packaging technologies.

About Teradyne

Teradyne (NASDAQ: TER) designs, develops, and manufactures automated test equipment and advanced robotics systems. Its test solutions for semiconductors and electronics products enable Teradyne’s customers to consistently deliver on their quality standards. Its advanced robotics business includes collaborative robots and mobile robots that support manufacturing and warehouse operations for companies of all sizes. For more information, visit teradyne.com. Teradyne® is a registered trademark of Teradyne, Inc., in the U.S. and other countries.

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